Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures
Author:
Affiliation:
1. Dept. of Information and Computer Science, Keio University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E104.C/6/E104.C_2020LHP0002/_pdf
Reference22 articles.
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2. [2] M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, “12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14µW Operation at 200MHz,” 2019 IEEE International Solid-State Circuits Conference-(ISSCC), pp.202-204, Feb. 2019. 10.1109/isscc.2019.8662431
3. [3] L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K. Bertels, and M. Alfailakawi, “Non-volatile look-up table based FPGA implementations,” 2016 11th International Design Test Symposium (IDT), pp.165-170, Dec. 2016. 10.1109/idt.2016.7843034
4. [4] T. Ikezoe, H. Amano, J. Akaike, K. Usami, M. Kudo, K. Hiraga, Y. Shuto, and K. Yagami, “A coarse grained-reconfigurable accelerator with energy efficient mtj-based non-volatile flip-flops,” 2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, pp.1-6, Dec. 2018. 10.1109/reconfig.2018.8641712
5. [5] S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications,” 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG), pp.17-20, Sept. 2012. 10.1109/iscdg.2012.6360000
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