Affiliation:
1. Department of Physical Electronics, Tokyo Institute of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Reference15 articles.
1. [1] Y. Chiu, P.R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol.39, no.12, pp.2139-2151, Dec. 2004.
2. [2] Y.-J. Kim, H.-C. Choi, K.-H. Lee, G.-C. Ahn, S.-H. Lee, J.-H. Kim, K.-J. Moon, M. Choi, K.-H. Moon, H.-J. Park, and B.-H. Park, “A9.43-ENOB 160 MS/s 1.2 V 65 nm CMOS ADC based on multi-stage amplifiers,” Proc. CICC, 2009, pp.271-274, Sept. 2009.
3. [3] D.-L. Shen and T.-C. Lee, “A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers,” IEEE J. Solid-State Circuits, vol.42, issue. 2, pp.258-268, Feb. 2007.
4. [4] F.-C. Hsieh and T.-C. Lee, “A 6-bit pipelined analog-to-digital converter with current-switching open-loop residue amplification,” IEEE Asian. Solid-State Circuits Conference, pp.61-64, Nov. 2008.
5. [5] C. Wulff and T. Ytterdal, “Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology,” Norchip, pp.1-4, Nov. 2007.