Delay Defect Diagnosis Methodology Using Path Delay Measurements-Reference-Cited by-同舟云学术

Delay Defect Diagnosis Methodology Using Path Delay Measurements

Published:2015 Issue:10 Volume:E98.C Page:991-994
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

JANG Eun Jung¹,CHUNG Jaeyong²,ABRAHAM Jacob A.¹

Affiliation:

1. Department of Electrical and Computer Engineering, The University of Texas

2. Department of Electronic Engineering, Incheon National University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E98.C/10/E98.C_991/_pdf

Reference13 articles.

1. [1] Y.-Y. Chen, M.-P. Kuo, and J.-J. Liou, “Diagnosis framework for locating failed segments of path delay faults,” In Test Conference, 2005, ITC 2005, IEEE International, pp.387-394, 2005.

2. [2] Y.-Y. Chen and J.-J. Liou, “Diagnosis framework for locating failed segments of path delay faults,” IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst., vol.16, no.6, pp.755-765, 2008.

3. [3] Y.-Y. Chen and J.-J. Liou, “A non-intrusive and accurate inspection method for segment delay variabilities,” In Asian Test Symposium, 2009, ATS'09, pp.343-348, IEEE, 2009.

4. [4] J.G. Dastidar and N.A. Touba, “A systematic approach for diagnosing multiple delay faults,” In Defect and Fault Tolerance in VLSI Systems, 1998, Proceedings., 1998 IEEE International Symposium on, pp.211-216, IEEE, 1998.

5. [5] J. Ghosh-Dastidar and N.A. Touba, “Adaptive techniques for improving delay fault diagnosis,” In VLSI Test Symposium, 1999, VTS'99, pp.168-172, IEEE, 1999.