Reducing the Standby Power Consumption of the S3 State for PCs
Author:
Affiliation:
1. Graduate Institute of Applied Science and Engineering, Fu Jen Catholic University
2. Department of Electrical Engineering, Fu Jen Catholic University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E98.C/10/E98.C_952/_pdf
Reference33 articles.
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3. [3] D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai, “Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution,” 33rd European Solid State Circuits Conference, pp.190-193, Sept. 2007.
4. [4] B.-D. Yang, Y.-K. Lee, S.-W. Sung, J.-J. Min, J.-M. Oh, and H.-J. Kang, “A Low Power Content Addressable Memory Using Low Swing Search Lines,” IEEE Transactions on Circuits and Systems, vol.58, no.12, pp.2849-2858, Dec. 2011.
5. [5] W. Quan, L. Zhe, W. Ping, and W. Min, “Design and Implementation of Low Power Consumption Wireless Pressure Transmitter Monitoring System,” International Conference on Computational Intelligence and Software Engineering, pp.1-5, Dec. 2009.
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1. New standby power targets;Energy Efficiency;2018-06-22
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