Affiliation:
1. Kumoth National Instisute of Technology
2. Top Engineering Co. Ltd.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Reference6 articles.
1. [1] MIPI Alliance, MIPI Alliance Specification for D-PHY, version 1.2, Sept. 2014.
2. [2] G. Balamurugan, J. Kennedy, G. Banerjee, J.E. Jaussi, M. Mansuri, F. O'Mahony, B. Casper, and R. Mooney, “A scalable 5-15 Gbps, 14-75 mW low-power I/O transceiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol.43, no.4, pp.1010-1019, April 2008. 10.1109/jssc.2008.917522
3. [3] S. Kim, Y. Jeong, M. Lee, K.-W. Kwon, and J.-H. Chun, “A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator,” IEEE J. Solid-State Circuits, vol.61, no.1, pp.213-225, Jan. 2014. 10.1109/tcsi.2013.2262186
4. [4] Meticom GmbH, 5 Channel FPGA to MIPI D-PHY Bridge IC MC20902 datasheet, version 1.07, Aug. 2016.
5. [5] S. Saxena, R.K. Nandwana, and P.K. Hanumolu, “A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,” IEEE J. Solid-State Circuits, vol.49, no.8, pp.1827-1836, Aug. 2014. 10.1109/jssc.2014.2317142
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 2.56-Gsymbol/s/lane MIPI C-PHY Transmission Bridge Chip for FPGA-based Pattern Generator;The Journal of Korean Institute of Information Technology;2024-07-31
2. A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2019-06-01