Highly Reliable and Drivability-Enhanced MOS Transistors with Rounded Nanograting Channels-Reference-Cited by-同舟云学术

Highly Reliable and Drivability-Enhanced MOS Transistors with Rounded Nanograting Channels

Published:2010 Issue:11 Volume:E93-C Page:1638-1644
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

ITO Takashi¹,ZHU Xiaoli¹,KUROKI Shin-Ichiro¹,KOTANI Koji¹

Affiliation:

1. Tohoku University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E93.C/11/E93.C_11_1638/_pdf

Reference23 articles.

1. High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

2. [2] E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, and M. Kakumu, “High performance 30nm bulk CMOS for 65nm technology node (CMOS5), ” IEDM Tech. Dig., pp.655-658, 2002.

3. [3] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, “15nm gate length planar CMOS transistor, ” IEDM Tech. Dig., pp.937-939, 2001.

4. [4] A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, H. Yoshimura, K. Miyano, N. Yasutake, H. Suto, K. Adachi, H. Fukui, T. Watanabe, N. Tamaoki, Y. Toyoshima, and H. Ishiuchi, “14nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide, ” IEDM Tech. Dig., pp.639-642, 2002.

5. [5] N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, and H. Ishiuchi, “A hp22nm node low operating power (LOP) technology with sub-10nm gate length planar bulk CMOS devices, ” VLSI Tech. Dig., pp.84-85, 2004.