Effects of Rapid Thermal Annealing on Poly-Si TFT with Different Gate Oxide Thickness-Reference-Cited by-同舟云学术

Effects of Rapid Thermal Annealing on Poly-Si TFT with Different Gate Oxide Thickness

Published:2010 Issue:1 Volume:E93-C Page:151-153
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

FAN Ching-Lin¹,LIN Yi-Yan²,YANG Yan-Hang²,CHEN Hung-Che²

Affiliation:

1. Department of Electronic Engineering, and Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology

2. Department of Electronic Engineering, National Taiwan University of Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E93.C/1/E93.C_1_151/_pdf

Reference10 articles.

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2. [2] P.S. Lin and T.S. Li, “The impact of scaling-down oxide thickness on poly-Si thin-film transistors: I-V characteristics,” IEEE Electron Device Lett., vol.15, no.4, pp.138-139, 1994.

3. [3] S.W. Lee, E. Kim, S.S. Han, H.S. Lee, D.C. Yun, K.M. Lim, M.S. Yang, and C.D. Kim, “Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide,” IEEE Electron Devices Lett., vol.24, no.3, pp.174-176, 2003.

4. [4] C.H. Kao, C.S. Lai, and C.L. Lee, “Oxide grown on polycrystal silicon by rapid thermal oxidation in N₂O,” J. Electrochem. Soc., vol.153, no.2, pp.G128-G133, 2006.

5. [5] H. Ueno, Y. Sugawara, H. Yano, T. Hatayama, Y. Uraoka, T. Fuyuki, and T. Serikawa, “Reliability of low temperature polycrystalline silicon thin-film transistors with ultrathin gate oxide,” Jpn. J. Appl. Phys., vol.46, no.7A, pp.4021-4027, 2007.

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