An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Author:
Affiliation:
1. Graduate School of Information Sciences, Tohoku University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://www.jstage.jst.go.jp/article/transele/E93.C/8/E93.C_8_1338/_pdf
Reference17 articles.
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2. [2] Gated clock conversion with Synplicity's synthesis products, July 2003.
3. [3] Y. Zhang, J. Roivainen, and A. Mammela, “Clock-gating in FPGAs: A novel and comparative evaluation,” Proc. EUROMICRO Conference on Digital System Design (DSD'06), pp.584-590, 2006.
4. An asynchronous dataflow FPGA architecture
5. [5] R. Manohar, “Reconfigurable asynchronous logic,” Proc. IEEE Custom Integrated Circuits Conference, pp.13-20, 2006.
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