On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform-Reference-Cited by-同舟云学术

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform

Published:2009 Issue:3 Volume:E92-C Page:356-363
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

SHIMANO Hiroki¹,MORISHITA Fukashi¹,DOSAKA Katsumi¹,ARIMOTO Kazutami¹

Affiliation:

1. System Core Technology Div., Renesas Technology Corp.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E92.C/3/E92.C_3_356/_pdf

Reference13 articles.

1. [1] T. Hattori, T. Irita, M. Ito, E. Yamamoto, H. Kato, G. Sado, T. Yamada, K. Nishiyama, H. Yagi, T. Koike, Y. Tsuchihashi, M. Higashida, H. Asano, I. Hayashibara, K. Tatezawa, Y. Shimazaki, N. Morino, K. Hirose, S. Tamaki, S. Yoshioka, R. Tsuchihashi, N. Arai, T. Akiyama, and K. Ohno, “A power management scheme controlling 20 power domains for a single-chip mobile processor, ” ISSCC Digest of Technical Papers, pp.542-543, 2006.

2. [2] M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osada, “A 300MHz 25µA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor, ” ISSCC Digest of Technical Papers, pp.494-495, 2004.

3. [3] M. Iida, N. Kuroda, H. Otsuka, M. Hirose, Y. Yamasaki, K. Ohta, K. Shimakawa, T. Nakabayashi, H. Yamauchi, T. Sano, T. Gyoten, M. Maruta, A. Yamazaki, F. Morishita, K. Dosaka, M. Takeuchi, and K. Arimoto, “A 322MHz random-cycle embedded DRAM with high-accueacy sensing and tuning, ” JSSCC, vol.40, no.11, pp.2296-2304, 2005.

4. [4] F. Morishita, I. Hayashi, H. Matsuoka, K. Takahashi, K. Shigeta, T. Gyoten, M. Niiro, H. Noda, M. Okamoto, A. Hachisuka, A. Amo. H. Shinkawata, T. Kasaoka, K. Dosaka, and K. Arimoto, “A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile application, ” JSSCC, vol.40, no.1, pp.204-212, 2005.

5. [5] Y. Taito, T. Tanizaki, M. Kinoshita, F. Igaue, T. Fujino, and K. Arimoto, “A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write, ” JSSCC, vol.38, no.11, pp.1967-1973, 2003.