Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device

Author:

HANZAWA Satoru1,HANYU Takahiro1

Affiliation:

1. Research Institute of Electrical Communication, Tohoku University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. [1] S. Matsunaga, K. Hiyama, A. Matsumoto, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu, “Standby-power-free compact ternary content-addressable memory cell chip using magnetic tunnel junction devices,” Appl. Phys. Express, vol.2, 023004, 2009.

2. [2] Y.-D. Kim, H.-S. Ahn, J.-Y. Park, S. Kim, and D.-K. Jeong, “A storage- and power-efficient range-matching TCAM for packet classification,” ISSCC Dig Tech. Papers, pp.587-588, Feb. 2006.

3. [3] S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, “A dynamic CAM based on a one-hot-spot block code for millions-entry lookup,” Symp. VLSI Circuit Dig. Tech. Papers, pp.382-385, June 2004.

4. [4] H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H.J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, “A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture,” ISSCC Dig Tech. Papers, pp.208-209, Feb. 2004.

5. [5] H. Noda, K. Dosaka, F. Morishita, and K. Arimoto, “A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM,” Proc. IEEE CICC, pp.451-454, 2005.

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