Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications
Author:
Affiliation:
1. Dept. of Electronic Engineering, National United University
2. IP Technology Service Group, Powerchip Technology Corporation
3. Device Engineering Group, Maxchip Technology Corporation
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E101.C/3/E101.C_143/_pdf
Reference56 articles.
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4. [4] V. Tomasevic, A. Boyer, S. Bendhia, A. Steinmair, B. Weiss, E. Seebacher, and P. Rust, “Coupling study in smart power mixed ICs with a dedicated on-chip sensor,” IEEE International Symposium on Electromagnetic Compatibility (EMC), pp.628-633, 2015. 10.1109/isemc.2015.7256236
5. [5] H. Zou, Y. Moursy, R. Iskander, J.P. Chaput, M.M. Louërat, C. Stefanucci, P. Buccela, M. Kayal, J.-M. Sallese, T. Gneiting, H. Alius, A. Steinmair, and E. Seebacher, “A CAD integrated solution of substrate modeling for industrial IC design,” 20th International Mixed-Signal Testing Workshop (IMSTW), pp.1-6, 2015. 10.1109/ims3tw.2015.7177885
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