1. [1] C.-Y. Lu, K.-Y. Hsieh, and R. Liu, “Future challenge of flash memory technologies,” Microelectronic Engineering, vol.86, pp.283-286, 2009.
2. [2] J.-D. Choe, K.H. Yeo, Y.J. Ahn, J.J. Lee, S.-H. Lee, B.Y. Choi, S.K. Sung, E.S. Cho, C.-H. Lee, D.-W. Kim, I. Chung, D. Park, and B.-I. Ryu, “Low voltage Program/Erase characteristics of Si nanocrystal memory with damascene gate FinFET on bulk Si wafer,” J. Semiconductor Technology and Science, vol.6, no.2, pp.68-73, 2006.
3. [3] R. Ranica, A. Villaret, P. Mazoyer, S. Monfray, D. Chanemougame, P. Masson, A. Regnier, C.N. Dray, R. Bez, and T. Skotnicki, “A new 40-nm SONOS structure based on backside trapping for nanoscale memories,” IEEE Trans. Nanotechnol., vol.4, no.5, pp.581-587, 2005.
4. [4] W.Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J.K. Liu, “Compact Nano-Electro-Mechanical Non-volatile Memory (NEMory) for 3D integration,” IEDM Tech. Dig., pp.603-606, 2007.
5. [5] W.W. Jang, J.O. Lee, J.-B. Yoon, M.-S. Kim, J.-M. Lee, S.-M. Kim, K.-H. Cho, D.-W. Kim, D. Park, and W.-S. Lee, “Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap,” Appl. Phys. Lett., vol.92, 103110, 2008.