An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
Author:
Affiliation:
1. Kobe University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E98.C/6/E98.C_489/_pdf
Reference19 articles.
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2. [2] S. O'Driscoll, K. V. Shenoy, and T. H. Meng, “Adaptive resolution ADC array for an implantable neural sensor,” IEEE Trans. Biomed. Circuits Syst., vol.5, no.2, pp.120–130, Apr. 2011.
3. [3] C. S. Taillefer and G. W. Roberts, “Delta-sigma A/D conversion via time-mode signal processing,” IEEE Trans. Circuits Syst. I, vol.56, no.9, pp.1908–1920, Sept. 2009.
4. [4] A. R. Macpherson, K. A. Townsend, and J. W. Haslett, “A 2.5 GS/s 3-bit time-based ADC in 90 nm CMOS,” ISCAS, pp.9–12, May 2011.
5. [5] A. R. Macpherson, J. W. Haslett, and L. Belostotski, “A 5 GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy,” CICC, pp.1–4, Sept. 2013.
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