VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition

Author:

NOGUCHI Hiroki1,MIURA Kazuo1,FUJINAGA Tsuyoshi1,SUGAHARA Takanobu1,KAWAGUCHI Hiroshi1,YOSHIMOTO Masahiko1

Affiliation:

1. Kobe University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference9 articles.

1. [1] K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “A low memory bandwidth Gaussian mixture model (GMM) processor for 20,000-word real-time speech recognition FPGA system,” Proc. IEEE Intl. Conf. on Field-Programmable Technology (FPT), pp.341-344, Dec. 2008.

2. [2] T. Fujinaga, K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “Parallelized Viterbi processor for 5,000-word large-vocabulary real-time continuous speech recognition FPGA system,” Proc. ISCA Annual Conf. of Intl. Speech Communication Association (Interspeech), pp.1483-1486, Sept. 2009.

3. [3] A. Lee, T. Kawahara, and K. Shikano, “Julius — An open source real-time large vocabulary recognition engine,” Proc. European Conf. on Speech Communication and Technology (EUROSPEECH), pp.1691-1694, Sept. 2001.

4. [4] E.C. Lin, K. Yu, R.A. Rutenbar, and T. Chen, “A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA,” Proc. 2007 ACM/SIGDA 15th Intl. Symposium on Field Programmable Gate Arrays (FPGA), pp.60-68, Feb. 2007.

5. [5] E.C. Lin and R.A. Rutenbar, “A multi-FPGA 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer,” Proc. ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA), pp.83-92, Feb. 2009.

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