Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder-Reference-Cited by-同舟云学术

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder

Published:2011 Issue:4 Volume:E94-C Page:439-447
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

ZHOU Jinjia¹,ZHOU Dajiang¹,HE Gang¹,GOTO Satoshi¹

Affiliation:

1. Graduate School of Information, Production and Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E94.C/4/E94.C_4_439/_pdf

Reference15 articles.

1. [1] Joint Video Team (JVT) of ITU-T VCEG and ISO/IEC MPEG, Draft ITU-T recommendation and final draft international standard of joint video specification ITU-T Rec. H.264/ISO/IEC 14496-10 AVC, May 2003.

2. [2] D. Zhou, Z. You, J. Zhu, J. Kong, Y. Hong, X. Chen, X. He, C. Xu, H. Zhang, J. Zhou, N. Deng, P. Liu, and S. Goto, “A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective,” Symposium on VLSI Circuits, pp.262-263, 2009.

3. [3] S. Wang, T. Lin, T. Liu, and C. Lee, “A new motion compensation design for H.264/AVC decoder,” IEEE International Symposium on Circuits and Systems, pp.4558-4561, 2005.

4. [4] D. Zhou and P. Liu, “A hardware-efficient dual-standard VLSI architecture for mc interpolation in AVS and H.264,” IEEE International Symposium on Circuits and Systems, pp.2910-2913, 2007.

5. [5] Y. Li, Y. Qu, and Y. He, “Memory cache based motion compensation architecture for HDTV H.264/AVC decoder,” IEEE International Symposium on Circuits and Systems, pp.2906-2909, 2007.

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