Affiliation:
1. Department of Electronic Engineering, Sogang University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Reference5 articles.
1. [1] P. Sudeep and S. Fulvio, “Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery,” IEEE International Test Conference, pp.1-5, Nov. 2010.
2. [2] Y. Taur and T.H. Nign, Fundamentals of MODERN VLSI DEVICES, pp.226-228, Cambridge, 1998.
3. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
4. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
5. Fitted Elmore delay: a simple and accurate interconnect delay model