A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques-Reference-Cited by-同舟云学术

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

Published:2016 Issue:4 Volume:E99.C Page:481-490
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

CHANG Chia-Wen¹,LO Kai-Yu¹,IBRAHIM Hossameldin A.¹,SU Ming-Chiuan¹,CHU Yuan-Hua²,JOU Shyh-Jye¹

Affiliation:

1. Department of Electronics Engineering, National Chiao Tung University

2. Information and Communications Research Laboratories (ICL), Industrial Technology Research Institute (ITRI)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/4/E99.C_481/_pdf

Reference18 articles.

1. [1] B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications,” in Proc. IEEE Custom Integrated Circuits Conf., pp.395-402, May 1997.

2. [2] T.C. Lee and W.L. Lee, “A spur suppression technique for phase-locked frequency synthesizers,” ISSCC Dig. Tech. Papers, pp 2432-2441, Feb. 2006.

3. [3] C.F. Liang, H.H. Chen, and S.I. Liu, “Spur-suppression techniques for frequency synthesizers,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol.54, no.8, pp.653-657, Aug. 2007.

4. [4] J. Choi, W. Kim, and K. Lim, “A spur suppression technique using an edge-interpolator for a charge pump PLL,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.20, no.5, pp.969-973, May 2012.

5. [5] C.Y. Kuo, J.Y. Chang, and S.I. Liu, “A spur reduction technique for a 5-GHz frequency synthesizer,” IEEE Trans. Circuits Syst. I, vol.53, no.3, pp.526-533, March 2006.

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