Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process
Author:
Affiliation:
1. Institute of RF- & OE-ICs, Southeast University
2. Quantum Information Research Center, Southeast University
3. College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E102.C/11/E102.C_2019ECP5007/_pdf
Reference18 articles.
1. [1] L. Xiu, W.-T. Lin, and T.-T. Lee, “Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC,” IEEE J. Solid-State Circuits, vol.48, no.2, pp.441-445, 2013. 10.1109/jssc.2012.2223931
2. [2] Y.-C. Choi, Y.-J. Seong, Y.-J. Yoo, S.-K. Lee, M. Velazquez Lopez, and H.-J. Yoo, “Multi-Standard Hybrid PLL with Low Phase-Noise Characteristics for GSM/EDGE and LTE Applications,” IEEE Trans. Microw. Theory Techn., vol.63, no.10, pp.3254-3264, 2015. 10.1109/tmtt.2015.2469251
3. [3] J.-S. Lee, M.-S. Keel, S.-I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electron. Lett., vol.36, no.23, pp.1907-1908, 2000. 10.1049/el:20001358
4. [4] C. Eichenberger and W. Guggenbuhl, “On charge injection in analog MOS switches and dummy switch compensation techniques,” IEEE Trans. Circuits Syst., vol.37, no.2, pp.256-264, 1990. 10.1109/31.45719
5. [5] Y.-S. Choi and D.-H. Han, “Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.53, no.10. pp.1022-1025, 2006. 10.1109/tcsii.2006.882122
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