A Logarithmic Compression ADC Using Transient Response of a Comparator
Author:
Affiliation:
1. Department of Electrical Engineering and Electronics, College of Science and Engineering, Aoyama Gakuin University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E100.C/4/E100.C_359/_pdf
Reference10 articles.
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2. [2] S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D. Uwaerts, and J. Bogaerts, “A logarithmic response CMOS image sensor with on-chip calibration,” IEEE J. Solid-State Circuits, vol.35, no.8, pp.1146-1152, Aug. 2000.
3. [3] J.-J. Sit, and R. Sarpeshkar, “A micropower logarithmic A/D with offset and temperature compensation,” IEEE J. Solid-State Circuits, vol.39, no.2, pp.308-319, Feb. 2004.
4. [4] A. Basu, R.W. Robucci, and P.E. Hasler, “A low-power, compact, adaptive logarithmic transimpedance amplifier operating over seven decades of current,” IEEE Trans. Circuits & Syst. I: Regular Papers, vol.54, no.10, pp.2167-2177, Oct. 2007.
5. [5] M. Gu, and S. Chakrabartty, “Design of a programmable gain, temperature compensated current-input current-output CMOS logarithmic amplifier,” IEEE Trans. Biomed. Circuits & Syst., vol.8, no.3, pp.423-431, June 2014.
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