Applying Razor Flip-Flops to SRAM Read Circuits-Reference-Cited by-同舟云学术

Applying Razor Flip-Flops to SRAM Read Circuits

Published:2017 Issue:3 Volume:E100.C Page:245-258
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

JIMBO Ushio¹,YAMADA Junji²,SHIOYA Ryota³,GOSHIMA Masahiro⁴

Affiliation:

1. Department of Informatics, School of Multidisciplinary Sciences, SOKENDAI (The Graduate University for Advanced Studies)

2. Graduate School of Information Science and Technology, The University of Tokyo

3. Graduate School of Engineering, Nagoya University

4. Information Systems Architecture Science Research Division, National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E100.C/3/E100.C_245/_pdf

Reference22 articles.

1. [1] T. Hiramoto, K. Takeuchi, and A. Nishida, “Variability of characteristics in scaled MOSFETs” J. IEICE, vol.92, no.6, pp.416-426, June 2009 (in Japanese).

2. [2] A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer Science & Business Media, April 2006.

3. [3] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.24, no.12, pp.1859-1880, Dec. 2005.

4. [4] D. Ernst, N.S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, “Razor: A low-power pipeline based on circuit-level timing speculation,” Proc. 36th Annual IEEE/ACM Int'l Symp. Microarchitecture, pp.7-18, Dec. 2003.

5. [5] D. Bull, S. Das, K. Shivshankar, G. Dasika, K. Flautner, and D. Blaauw, “A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation,” IEEE Int'l Solid-State Circuits Conf. Dig. Tech. Papers, pp.284-285, Feb. 2010.

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