Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs-Reference-Cited by-同舟云学术

Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs

Published:2017 Issue:6 Volume:E100.C Page:576-583
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

SUGAWARA Mitsutoshi¹,XU Zule²,MATSUZAWA Akira¹

Affiliation:

1. Tokyo Institute of Technology

2. Tokyo University of Science

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E100.C/6/E100.C_576/_pdf

Reference8 articles.

1. [1] J.J. Corcoran, T. Hornak, and P.B. Skof, “A High-resolution Error Plotter for Analog-to-Digital Converters,” IEEE Trans. Instrumentation & Measurement, vol.IM-24, no.4, pp.370-374, Dec. 1975.

2. [2] J.R. Naylor, “Testing Digital/Analog and Analog/Digital Converters,” IEEE Trans. Circuits and Systems, vol.CAS-25, no.7, pp.526-538, July 1978.

3. [3] H.-W. Ting, B.-D. Liu, and S.-J. Chang, “A Histogram-Based Testing Method for Estimating A/D Converter Performance,” IEEE Trans. Instrumentation & Measurement, vol.57, no.2, pp.420-427, Feb. 2008.

4. [4] “Keysight Technologies B2961A/B2962A 6.5 Digit Low Noise Power Source Faster and easier 14-bit ADC evaluation,” Aug. 2014, http://vs1.textlab.io/store/data/000116402.pdf?key=e38832449ba228054d9fa57e75adc2b2&r=1&fn=116402.pdf&t=1470909235348&p=86400

5. [5] M. Ehsanian, B. Kaminska, and K. Arabi, “A New Digital Test Approach for Analog-to-Digital Converter Testing,” Proc. 14th VLSI Test Symposium, pp.60-65, 1996.