New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters

Author:

MORADI Mona1,FAGHIH MIRZAEE Reza2,NAVI Keivan34

Affiliation:

1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University

2. Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University

3. Faculty of Electrical and Computer Engineering, Shahid Beheshti University

4. School of Computer Science, Institute for Research in Fundamental Sciences (IPM)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference29 articles.

1. [1] L. Jinghong, J. Lijiu, J. Anping, and J. Song, “A new approach for high performance multiply-accumulator design,” Proc. 5th International Conference on ASIC, vol.2, pp.1293-1295, Oct. 2003.

2. [2] C.S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electronic Computers, vol.EC-13, no.1, pp.14-17, Feb. 1964.

3. [3] L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza, vol.34, pp.349-356, 1965.

4. [4] M. Moradi and K. Navi, “Performance Analysis of 3 Improved Modified 1-Bit Full Adder Cells Based on CNTFET Technology,” European Journal of Scientific Research, vol.62, no.4, pp.588-599, Oct. 2011.

5. [5] S. Mehrabi, R. Faghih Mirzaee, S. Zamanzadeh, K. Navi, and O. Hashemipour, “Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4≤m≤10) compressors,” International Journal of High Performance Systems Architecture, vol.4, no.4, pp.231-241, 2013.

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