1. [1] L. Jinghong, J. Lijiu, J. Anping, and J. Song, “A new approach for high performance multiply-accumulator design,” Proc. 5th International Conference on ASIC, vol.2, pp.1293-1295, Oct. 2003.
2. [2] C.S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electronic Computers, vol.EC-13, no.1, pp.14-17, Feb. 1964.
3. [3] L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza, vol.34, pp.349-356, 1965.
4. [4] M. Moradi and K. Navi, “Performance Analysis of 3 Improved Modified 1-Bit Full Adder Cells Based on CNTFET Technology,” European Journal of Scientific Research, vol.62, no.4, pp.588-599, Oct. 2011.
5. [5] S. Mehrabi, R. Faghih Mirzaee, S. Zamanzadeh, K. Navi, and O. Hashemipour, “Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4≤m≤10) compressors,” International Journal of High Performance Systems Architecture, vol.4, no.4, pp.231-241, 2013.