A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications-Reference-Cited by-同舟云学术

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications

Published:2016 Issue:6 Volume:E99.C Page:717-726
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

SHIBATA Nobutaro¹,GOTOH Yoshinori¹,ISHIHARA Takako¹

Affiliation:

1. NTT Microsystem Integration Laboratories, NTT Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/6/E99.C_717/_pdf

Reference18 articles.

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4. [4] H. Takahashi, S. Sato, G. Goto, T. Nakamura, H. Kikuchi, and T. Shirato, “A 240k transistor CMOS array with flexible allocation of memory and channels,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.124-125, Feb. 1985.

5. [5] H. Veendrick, D. van den Elshout, D. Harberts, and T. Brand, “An efficient and flexible architecture for high-density gate arrays,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.86-87, Feb. 1990.