A 7-bit 1-GS/s Flash ADC with Background Calibration

Author:

TSUKAMOTO Sanroku1,MIYAHARA Masaya1,MATSUZAWA Akira1

Affiliation:

1. Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference39 articles.

1. [1] T. Matsuura, et al., “A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter,” IEEE J. Solid-State Circuits, vol.33, pp.1840-1850, Nov. 1998.

2. [2] K. Okamoto, et al., “A fully integrated 0.13-µm CMOS mixed-signal SoC for DVD player applications,” IEEE J. Solid-State Circuits, vol.38, pp.1981-1991, Nov. 2003.

3. [3] M. Bathaee, et al., “A 0.13µm CMOS SoC for all format blue and red laser DVD front-end digital signal processor,” IEEE ISSCC Dig. Tech. Papers, pp.264-265, Feb. 2006.

4. [4] H. Yamaguchi, et al., “A 5Gb/s Transceiver with an ADC-Based Feedforward CDR and CMA Adaptive Equalizer in 65nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp.168-169, Feb. 2010.

5. [5] S. Verma, et al., “A 10.3GS/s 6b flash ADC for 10G Ethernet applications,” IEEE ISSCC Dig. Tech. Papers, pp.462-463, Feb. 2013.

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