Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs)
Author:
Affiliation:
1. Chuo University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E103.C/4/E103.C_2019CDP0006/_pdf
Reference24 articles.
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2. [2] K. Takeuchi, T. Tanaka, and T. Tanzawa, “A Multi-page Cell Architecture for High-speed Programming Multi-level NAND Flash Memories,” IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp.67-68, June 1997. 10.1109/vlsic.1997.623810
3. [3] S.-H. Shin, D.-K. Shim, J.-Y. Jeong, O.-K. Kwon, S.-Y. Yoon, M.-H. Choi, T.-Y. Kim, H.-W. Park, H.-J. Yoon, Y.-S. Song, Y.-H. Choi, S.-W. Shim, Y.-L. Ahn, K.-T. Park, J.-M. Han, K.-H. Kyung, and Y.-H. Jun, “A New 3-bit Programming Algorithm using SLC-to-TLC Migration for 8MB/s High Performance TLC NAND Flash Memory,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.132-133, June 2012. 10.1109/vlsic.2012.6243825
4. [4] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” IEEE Symp. VLSI Technology Dig. Tech. Papers, pp.14-15, June 2007. 10.1109/vlsit.2007.4339708
5. [5] https://www.crucial.com/usa/en/storage-ssd-p1
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