A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver-Reference-Cited by-同舟云学术

A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver

Published:2016 Issue:9 Volume:E99.C Page:1039-1047
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

TAKEMOTO Takashi¹,MATSUOKA Yasunobu²,YAMASHITA Hiroki²,NAKAMURA Takahiro²,LEE Yong²,ARIMOTO Hideo²,IDO Tatemi³

Affiliation:

1. Research & Development Group, Center for Exploratory Research, Hitachi, Ltd.

2. Research & Development Group, Center for Technology Innovation — Electronics, Hitachi, Ltd.

3. IT Platform Products Management Division, Hitachi, Ltd.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/9/E99.C_1039/_pdf

Reference21 articles.

1. [1] Cisco Visual Networking Index: The Zettabyte Era-Trends and Analysis, [Online]. Available: http://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/VNI_Hyperconnectivity_WP.html.

2. [2] Y. Chen, M. Kibune, A. Toda, A. Hayakawa, T. Akiyama, S. Sekiguchi, H. Ebe, N. Imaizumi, T. Akahoshi, S. Akiyama, S. Tanaka, T. Simoyama, K. Morito, T. Yamamoto, T. Mori, Y. Koyanagi, and H. Tamura, “A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI,” ISSCC Dig. Tech. Papers, pp.402-403, Feb. 2015.

3. [3] J. Proesel, C. Schow, and A. Rylyakov, “25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp.418-420, Feb. 2012.

4. [4] J.-Y. Jiang, P.-C. Chiang, H.-W. Hung, C.-L. Lin, T. Yoon, and J. Lee, “100Gb/s Ethernet Chipsets in 65nm CMOS Technology,” ISSCC Dig. Tech. Papers, pp.120-121, Feb. 2013.

5. [5] K. Yu, H. Li, C. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C.-H. Chen, M. Fiorentino, P.Y. Chiang, and S. Palermo, “A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization,” ISSCC Dig. Tech. Papers, pp.406-407, Feb. 2015.

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1. A 50-Gb/s High-Sensitivity (−9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18- $\mu$ m SiGe BiCMOS Technology;IEEE Journal of Solid-State Circuits;2018-05