An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing-Reference-Cited by-同舟云学术

An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing

Published:2016 Issue:3 Volume:E99.C Page:404-414
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

HSIEH Tong-Yu¹,WANG Tai-Ping²,YANG Shuo¹,HSU Chin-An¹,LIN Yi-Lung²

Affiliation:

1. Department of Electrical Engineering, National Sun Yat-sen University

2. ASE group

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/3/E99.C_404/_pdf

Reference10 articles.

1. [1] J. Rivoir, “Parallel test reduces cost of test more effectively than just a cheap tester,” Proc. Int'l. Electronics Manufacturing Technology Symp., pp.263-272, 2004.

2. [2] S.K. Goel and E.J. Marinissen, “On-chip test infrastructure design for optimal multi-site testing of system chips,” Proc. Design, Automation and Test in Europe, pp.44-49, 2005.

3. [3] V. Iyengar, S.K. Goel, K. Chakrabarty, and E.J. Marinissen, “Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints,” Proc. Int'l. Test Conf., pp.1159-1168, 2002.

4. [4] H. Vranken, T. Waayers, H. Fleury, and D. Lelouvier, “Enhanced reduced pin-count test for full scan design,” Proc. Int'l. Test Conf., pp.738-747, 2001.

5. [5] E.H. Volkerink, A. Khoche, J. Rivoir, and K.D. Hilliges, “Test economics for multi-site test with modern cost reduction techniques,” Proc. VLSI Test Symp., pp.411-416, 2002.

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