Fabrication of InP/InGaAs DHBTs with Buried SiO2 Wires-Reference-Cited by-同舟云学术

Fabrication of InP/InGaAs DHBTs with Buried SiO2 Wires

Published:2011 Issue:5 Volume:E94-C Page:830-834
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

TAKEBE Naoaki¹,KOBAYASHI Takashi¹,SUZUKI Hiroyuki¹,MIYAMOTO Yasuyuki¹,FURUYA Kazuhito¹

Affiliation:

1. Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E94.C/5/E94.C_5_830/_pdf

Reference7 articles.

1. InP buried growth of SiO2 wires toward reduction of collector capacitance in HBT

2. [2] H. Yamashita, T. Miura, S. Takahashi, Y. Miyamoto, and K. Furuya, “Fabrication of 200-nm-thick SiO₂ wires buried in InP for reduction in collector capacitance in InP/InGaAs DHBT,” Topical Workshop on Heterostructure Microelectronics, FrC-3, 2007.

3. [3] S. Takahashi, T. Miura, H. Yamashita, Y. Miyamoto, and K. Furuya, “DC characteristics of HBT with buried SiO₂ wires in collector” IEICE Technical Report, ED2007-37, 2007.

4. [4] N. Takebe, H. Yamashita, S. Takahashi, H. Saito, T. Kobayashi, Y. Miyamoto, and K. Furuya, “In-situ etching by CBr₄ in InP heterojunction bipolar transistors with buried SiO₂ wire,” IEICE Technical Report, ED2009-46, 2009.

5. [5] E. Lobisser, Z. Griffith, V. Jain, B.J. Thibeault, and M.J.W. Rodwell, “200-nm InGaAs/InP Type I DHBT Employing a Dual-Sidewall Emitter Process Demon-strating f_max > 800GHz and f_τ =360GHz,” Indium Phosphide and Related Materials, MA1.2, 2009.