Layout optimization methodology for ring-based on-chip optical network
Author:
Affiliation:
1. School of Telecommunications Engineering, Xidian University
2. School of Computer Science and Technology, Xidian University
3. School of Microelectronics, Xidian University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/16/20/16_16.20190458/_pdf
Reference30 articles.
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4. [4] J. Postman, et al.: “SWIFT: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21 (2013) 1432 (DOI: 10.1109/TVLSI.2012.2211904).
5. [5] S. Bayar and A. Yurdakul: “PFMAP: Exploitation of particle filters for network-on-chip mapping,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015) 2116 (DOI: 10.1109/TVLSI.2014.2360791).
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