Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges-Reference-Cited by-同舟云学术

Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

Published:2019 Issue:13 Volume:16 Page:20190218-20190218
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Niitsu Kiichi¹,Kobayashi Osamu²,Yamaguchi Takahiro J.³,Kobayashi Haruo²

Affiliation:

1. Graduate School of Engineering, Nagoya University

2. STARC

3. Graduate School of Engineering, Gunma University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/16/13/16_16.20190218/_pdf

Reference32 articles.

1. [1] Texas Instrument’s Production Introduction Page: http://www.ti.com/lsds/ti/clocks-timers/clock-jitter-cleaners-products.page.

2. [2] M. J. Underhill: US patent 6,791,393 B1 (Sep. 14, 2004).

3. [3] K. Niitsu, et al.: “A clock jitter reduction circuit using gated phase blending between self-delayed clock edges,” Proc. IEEE Symp. on VLSI Circuits (2012) 142 (DOI: 10.1109/VLSIC.2012.6243830).

4. [4] K. Niitsu, et al.: “Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges,” Proc. IEEE/ACM Asia and South Pacific Design Automation Conf. (2013) 103 (DOI: 10.1109/ASPDAC.2013.6509577).

5. [5] J. A. McNeill: “Jitter in ring oscillators,” IEEE J. Solid-State Circuits 32 (1997) 870 (DOI: 10.1109/4.585289).

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