Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Author:

Pan Chunhui1,San Hao1

Affiliation:

1. Tokyo City University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference31 articles.

1. [1] P. Harpe: “A compact 10-b SAR ADC with unit-length capacitors and a passive FIR filter,” IEEE J. Solid-State Circuits 54 (2019) 636 (DOI: 10.1109/JSSC.2018.2878830).

2. [2] S. Li, et al.: “A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure,” IEEE J. Solid-State Circuits 53 (2018) 3484 (DOI: 10.1109/JSSC.2018.2871081).

3. [3] S. Hsieh, et al.: “A 0.5-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization,” IEEE J. Solid-State Circuits 53 (2018) 2763 (DOI: 10.1109/JSSC.2018.2862880).

4. [4] W. Jiang, et al.: “A 7.6 mW 1 GS/s 60 dB SNDR single-channel SAR-assisted pipelined ADC with temperature-compensated dynamic Gm-R-based amplifier,” ISSCC Dig. Tech. Papers (2019) 60 (DOI: 10.1109/ISSCC.2019.8662524).

5. [5] A. ElShater, et al.: “A 10 mW 16 b 15 MS/s two-step SAR ADC with 95 dB DR using dual-deadzone ring-amplifier,” ISSCC Dig. Tech. Papers (2019) 70 (DOI: 10.1109/ISSCC.2019.8662400).

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