Design of CIC based decimation filter structure using FPGA for WiMAX applications
Author:
Affiliation:
1. Department of ECE, Sreenidhi Institute of Science and Technology (Autonomous) Hyderabad
2. Department of ECE, Sreenivasa Institute of Technology and Management Studies Autonomous
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/16/7/16_16.20190074/_pdf
Reference10 articles.
1. [1] M. Laddomada: “Generalized comb decimation filters for ΣΔ A/D converters: Analysis and design,” IEEE Trans. Circuits Syst. I, Reg. Papers 54 (2007) 994 (DOI: 10.1109/TCSI.2007.895528).
2. [2] S. Vijayakumar and R. Korah: “Circuit level, 32 nm, 1-bit MOSSI-ULP adder: Power, PDP and area efficient base cell for unsigned multiplier,” IEICE Electron. Express 11 (2014) 20140109 (DOI: 10.1587/elex.11.20140109).
3. [3] M. Laddomada: “Comb-based decimation filters for ΣΔ A/D converters: Novel schemes and comparisons,” IEEE Trans. Signal Process. 55 (2007) 1769 (DOI: 10.1109/TSP.2006.890822).
4. [4] G. J. Dolecek and F. Harris: “Design of CIC compensator filter in a digital IF receiver,” IEEE International Symp. Comm. and Info. Tech. (2008) 638 (DOI: 10.1109/ISCIT.2008.4700271).
5. [5] G. J. Dolecek and F. Harris: “On design of two-stage CIC compensation filter,” IEEE International Symposium - ISIE (2009) 903 (DOI: 10.1109/ISIE.2009.5213597).
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