A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process

Author:

Zhen Wenxiang12,Li Shaojun1,Cao Shurui12,Su Yongbo1,Jin Zhi1

Affiliation:

1. High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics of Chinese Academy of Sciences

2. School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference31 articles.

1. [1] N. Weiss, et al.: “DC-62 GHz 4-phase 25% duty cycle quadrature clock generator,” 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Miami USA (2017) (DOI: 10.1109/CSICS.2017.8240468).

2. [2] F. Herzel, et al.: “A 60 GHz frequency divider with quadrature outputs in 130 nm SiGe BiCMOS technology for optical OFDM systems,” 10th European Microwave Integrated Circuits Conference (2015) (DOI: 10.1109/EuMIC.2015.7345070).

3. [3] A. Zandieh, et al.: “A 2x-oversampling, 128-GS/s 5-bit flash ADC for 64-GBaud applications,” 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) (2018) (DOI: 10.1109/BCICTS.2018.8550990).

4. [4] A. Zandieh, et al.: “Design of a 55-nm SiGe BiCMOS 5-bit time-interleaved flash ADC for 64-Gbd 16-QAM fiberoptics applications,” IEEE J. Solid-State Circuits 54 (2019) 2375 (DOI: 10.1109/JSSC.2019.2917155).

5. [5] K.N. Madsen, et al.: “A high-linearity, 30 GS/s track-and-hold amplifier and time interleaved sample-and hold in an InP-on-CMOS process,” IEEE J. Solid-State Circuits 50 (2015) 2692 (DOI: 10.1109/JSSC.2015.2472642).

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