An improved segmented DAC for column readout circuit correction of large array CMOS image sensor-Reference-Cited by-同舟云学术

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Published:2020-05-25 Issue:10 Volume:17 Page:20200094-20200094
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Guo Zhongjie¹,Yu Ningmei¹,Wu Longsheng²

Affiliation:

1. School of Automation and Information Engineering, Xi’an University of Technology

2. Xi’an Microelectronic Technology Institute

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/10/17_17.20200094/_pdf

Reference33 articles.

1. [1] K.D. Choo, et al.: “Energy-efficient motion-triggered IoT CMOS image sensor with capacitor array-assisted charge-injection SAR ADC,” IEEE J. Solid-State Circuits 54 (2019) 2921 (DOI: 10.1109/jssc.2019.2939664).

2. [2] N. Sarhangnejad, et al.: “Dual-tap computational photography image sensor with per-pixel pipelined digital memory for intra-frame coded multi-exposure,” IEEE J. Solid-State Circuits 54 (2019) 3191 (DOI: 10.1109/JSSC.2019.2932623).

3. [3] Ø. Janbu, et al.: “A 1.17-megapixel CMOS image sensor with 1.5 A/D conversions per digital CDS pixel readout and four in-pixel gain steps,” IEEE J. Solid-State Circuits 54 (2019) 2568 (DOI: 10.1109/jssc.2019.2924337).

4. [4] K. Yasutomi, et al.: “A sub-100 μm-range-resolution time-of-flight range image sensor with three-tap lock-in pixels, non-overlapping gate clock, and reference plane sampling,” IEEE J. Solid-State Circuits 54 (2019) 2291 (DOI: 10.1109/jssc.2019.2916310).

5. [5] R.K. Henderson, et al.: “A 192×128 time correlated SPAD image sensor in 40-nm CMOS technology,” IEEE J. Solid-State Circuits 54 (2019) 1907 (DOI: 10.1109/jssc.2019.2905163).