A local congestion elimination technique driven by overflow-Reference-Cited by-同舟云学术

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A local congestion elimination technique driven by overflow

Published:2020-09-10 Issue:17 Volume:17 Page:20200232-20200232
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Wu Wei¹,Di Zhixiong¹,Shi Jiangyi²,Feng Quanyuan¹,Tang Zhengguang²

Affiliation:

1. The School of Information Science and Technology, Southwest Jiaotong University

2. The School of Microelectronics, Xidian University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/17/17_17.20200232/_pdf

Reference30 articles.

1. [1] D.Z. Pan, et al.: “Design for manufacturing with emerging nanolithography,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 32 (2013) 1453 (DOI: 10.1109/TCAD.2013.2276751).

2. [2] A. Jahanian and M.S. Zamani: “Metro-on-chip: an efficient physical design technique for congestion reduction,” IEICE Electron. Express 4 (2007) 510 (DOI: 10.1587/elex.4.510).

3. [3] C.J. Alpert, et al.: “What makes a design difficult to route,” Proc. ISPD (2010) 7 (DOI: 10.1145/1735023.1735028).

4. [4] Z. Li, et al.: “Guiding a physical design closure system to produce easier-to-route designs with more predictable timing,” Proc. DAC (2012) 465 (DOI: 10.1145/2228360.2228442).

5. [5] W.-T.J. Chan, et al.: “BEOL stack-aware routability prediction from placement using data mining techniques,” Proc. ICCD (2016) 41 (DOI: 10.1109/ICCD.2016.7753259).

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