High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field-Reference-Cited by-同舟云学术

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

Published:2013 Issue:4 Volume:10 Page:20130057-20130057
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yang Xiaoming¹,Li Tianqian¹,Cai Yu²,Wang Jun¹,Chen Changjiang¹

Affiliation:

1. School of Electrical and Information, Research Center for Advanced Computation, Xihua University

2. Chengdu Textile College

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/10/4/10_10.20130057/_pdf

Reference5 articles.

1. [1] S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of high break-down voltage (>700V) in thin SOI devices,” Proc. 3rd Conf. IEEE ISPSD, Baltimore, USA, 146060, pp. 31-35, April 1991.

2. [3] X. Luo, B. Zhang, Z. Li, Y. Guo, X. Tang, and Y. Liu, “A novel 700-V SOI LDMOS with double-sided trench,” IEEE Electron Device Lett., vol. 28, no. 5, pp. 422-424, 2007.

3. [4] X. Luo, Z. Li, B. Zhang, Y. Guo, and X. Tang, “A novel structure and its breakdown mechanism of a SOI high voltage device with a shielding trench,” Chin. J. Semicond., vol. 26, no. 11, pp. 2154-2158, 2005.

4. [5] H. Funaki, Y. Yamaguchi, K. Hirayama, and A. Nakagawa, “New 1200V MOSFET structure on SOI with SIPOS shielding layer,” Proc. 10th Conf. IEEE ISPSD, Kyoto, Japan, 702621, pp. 25-28, Aug. 1998.

5. [7] Z. Wang, B. Zhang, Q. Fu, G. Xie, and Z. Li, “An L-Shaped Trench SOI-LDMOS With Vertical and Lateral Dielectric Field Enhancement,” IEEE Electron Device Lett., vol. 33, no. 5, pp. 703-705, 2012.

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