Hierarchical round-robin mapper emulator for evaluating massively parallel Ethernet physical layer developing

Author:

Sugiura Kyosuke1,Murakami Masaki1ORCID,Uematsu Yoshihiko1,Okamoto Satoru1ORCID,Yamanaka Naoaki1ORCID

Affiliation:

1. Graduate School of Science and Technology, Keio University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

General Medicine

Reference5 articles.

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2. [2] K. Sugiura, M. Murakami, S. Okamoto, and N. Yamanaka, “Architecture of dynamic MAC using bit-by-bit mapping on massively parallel optical channels,” Proc. 15th International Conference on IP+Optical Network (iPOP 2019), Kawasaki, Japan, T3-4, May 2019.

3. [3] S. Okamoto, K. Sugiura, M. Murakami, E. Oki, and N. Yamanaka, “Research on dynamic MAC technologies for future massively parallel and sliced optical networks,” IEICE Technical Report, PN2019-25, pp. 7-14, Nov. 2011 (in Japanese).

4. [4] N.D. Matsakis and F.S. Klock, “The rust language,” Proc. 2014 ACM SIGAda Annual Conference on High Integrity Language Technology (HILT ’14), New York, NY, USA, pp. 103-104, Oct. 2014. DOI: 10.1145/2663171.2663188K

5. [5] R.D. Blumofe and C.E. Leiserson, “Scheduling multithreaded computations by work stealing,” Journal of the ACM, vol. 46, no. 5, pp. 720-748, Sept. 1999. DOI: 10.1145/324133.324234

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1. Experiment of Nationwide Multi-Route Skew Cancelling for Dynamic Mapping of MAC Signals over SDM/WDM Network Testbed;2022 27th OptoElectronics and Communications Conference (OECC) and 2022 International Conference on Photonics in Switching and Computing (PSC);2022-07-03

2. Lane alignment characteristics in massively parallel Ethernet-based transmission systems;IEICE Communications Express;2022-02-01

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