Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip-Reference-Cited by-同舟云学术

Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip

Published:2009 Issue:1 Volume:6 Page:1-7
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Janidarmian Majid¹,Khademzadeh Ahmad²,Tavanpour Misagh¹

Affiliation:

1. CE Department, Islamic Azad University, Science & Research Branch

2. Iran Telecom Research Center

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/6/1/6_1_1/_pdf

Reference7 articles.

1. [1] S. Kumar, A. Jantsch, J. P. Sonioen, M. Forsell, M. Millberg, J. Oeberg, K. Tiensirja, and A. Hemani, “A network on chip architecture and design methodology, ” IEEE Symp. VLSI ISVLSI02, pp. 105-112, Pittzburg, USA, April 2002.

2. [2] Umit Y. Ogras and J. Hu, “Key Research Problems in NoC Design: A Holistic Perspective, ” Proc. CODES+ISSS'05, New Jersey, USA, pp. 69-74, Sept. 19-21, 2005.

3. [3] S. Murali and G. De Micheli, “Bandwidth Constrained Mapping of Cores onto NoC Architectures, ” Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), vol. 2, pp. 896-901, Feb. 2004.

4. [4] T. Shen, C. H. Chao, Y. K. Lien, and A.Y. Wu, “A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-based on-chip Network, ” Proceedings of the First International Symposium Networks-on-Chip (NOCS'07), pp.317-322, May 2007.

5. [5] Jingcao Hu and Radu Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints, ” Asia and South Pacific Proceedings of the ASP-DAC on Design Automation Conference, 21-24, pp. 233-239, Jan. 2003.

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