Brain-Like Vision Systems Using Merged Analog-Digital LSI Architecture-Reference-Cited by-同舟云学术

Brain-Like Vision Systems Using Merged Analog-Digital LSI Architecture

Published:2007 Issue:1 Volume:1 Page:19-29
ISSN:1882-0875
Container-title:IEICE ESS Fundamentals Review
language:en
Short-container-title:IEICE Fundamentals Review

Author:

MORIE Takashi¹

Affiliation:

1. Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

General Earth and Planetary Sciences,General Environmental Science

Link

http://www.jstage.jst.go.jp/article/essfr/1/1/1_1_1_19/_pdf

Reference38 articles.

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2. (2)J. Tanabe, Y. Taniguchi, T. Miyamori, Y. Miyamoto, H. Takeda, M. Tarui, H. Nakayama, N. Takeda, K. Maeda, and M. Matsui, “Visconti: Multi-VLIW image recognition processor based on configurable processor,” Proc. of IEEE Custom Integrated Circuits Conference, pp.185-188, 2003.

3. (3) T. Shiota, K. Kawasaki, Y. Kawabe, W. Shibamoto, A. Sato, T. Hashimoto, F. Hayakawa, S. Tago, H. Okano, Y. Nakamura, H. Miyake, A. Suga, and H. Takahashi, “A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quardruple 8-Way VLIW processors,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp.194-195, 2005.

4. (4) M. Nakajima, H. Noda, K. Dosaka, K. Nakata, M. Higashida, O. Yamamoto, K. Mizumoto, H. Kondo, Y. Shimazu, K. Arimoto, K. Saitoh, and T. Shimizu,“A 40GOPS 250mW massively parallel processor based on matrix architecture,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp.410-411, 2006.

5. (5) “九州工業大学,21 世紀COE プログラム「生物とロボットが織りなす脳情報工学の世界」,” http://www.brain.kyutech.ac.jp/coe21/index.html