Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP-Reference-Cited by-同舟云学术

Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP

Published:2013 Issue:2 Volume:E96.A Page:495-504
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KAIZU Tomohiro¹,ISOBE Yoshinao²,SUZUKI Masato¹

Affiliation:

1. Japan Advanced Institute of Science and Technology

2. National Institute of Advanced Industrial Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/2/E96.A_495/_pdf

Reference10 articles.

1. [1] C.A.R. Hoare, Communicating Sequential Processes, Prentice Hall, 1985.

2. [2] A.W. Roscoe, The Theory and Practice of Concurrency, Prentice Hall, 1998.

3. [3] Formal Systems (Europe) Limited, “FDR2 User Manual,” http://www.fsel.com/fdr2_manual.html.

4. [4] B. Buth and M. Schronen, “Model-checking the architectural design of a fail-safe communication system for railway interlocking systems,” J.M. Wing, J. Woodcock, and J. Davies, ed., FM99, LNCS 1709, pp.1869-1869, Springer, 1999.

5. [5] P. Ryan, S. Schneider, M. Goldsmith, G. Lowe, and B. Roscoe, The modelling and analysis of security protocols: the csp approach, Addison-Wesley, 2001.

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