Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm

Author:

CHEN Ming-Chih1,HSIAO Shen-Fu2

Affiliation:

1. National Kaohsiung First University of Science and Technology

2. National Sun Yat-Sen University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference15 articles.

1. [1] “Advanced encryption standard (AES), ” FIPS Publication 197, Nov. 26, 2001. Available at http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

2. [2] H. Kuo and I. Verbauwhede, “Architectural optimization for a 1.82Gbits/sec VLSI implementation of the AES rijndael algorithm, ” Proc. Cryptographic Hardware and Embedded Systems, pp.51-64, May 2001.

3. [3] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact rijndael hardware architecture with S-box optimization, ” Advanced in Cryptography-ASIACRYPT 2001, pp.239-254, Dec. 2001.

4. [4] C.C. Lu and S.Y. Tseng, “Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter, ” Proc. Application-Specific Systems, Architectures and Processors, pp.277-285, July 2002.

5. Architectures and VLSI implementations of the AES-Proposal Rijndael

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