Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Reference34 articles.
1. [1] B. Razavi, “Design of monolithic phase-locked loops and clock recovery circuits — A tutorial,” in Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, B. Razavi, ed., pp.1-39, IEEE Press, New York, 1996. 10.1109/9780470545331.ch1
2. [2] D.B. Talbot, “A review of PLL fundamentals,” in Frequency Acquisition Techniques for Phase Locked Loops, pp.3-15, IEEE, 2012. 10.1002/9781118383285.ch2
3. [3] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai “Spread-spectrum clock generator for serial ATA with multi-bit ΣΔ modulator-controlled fractional PLL,” IEICE Trans Electron., vol.E89-C, no.11, pp.1682-1688, Nov. 2006. 10.1093/ietele/e89-c.11.1682
4. [4] S-H. Cho and A.P. Chandrakasan, “A 6.5GHz CMOS FSK modulator for wireless sensor applications,” 2002 Symposium on VLSI Circuits. Digest of Technical Papers, pp.182-185, June 2002. 10.1109/vlsic.2002.1015079
5. [5] C. Lu, J. Liu, J. Bao, S-L.C. Chen, P. Yue, J. Chen, and C-M. Chien “A multi-mode transmitter supporting BT/BLE and 802.11b/g/n/ax for IoT applications,” 2021 IEEE 7th World Forum on Internet of Things (WF-IoT), pp.25-28, June 2021. 10.1109/wf-iot51360.2021.9595148