A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures
Author:
Affiliation:
1. Dept. of Computer Science and Communications Engineering, Waseda University
2. Dept. of Electronic and Photonic Systems, Waseda University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E98.A/7/E98.A_1366/_pdf
Reference23 articles.
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2. [2] J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, “Architecture and synthesis for on-chip multi-cycle communication,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.23, no.4, pp.550-564, 2004.
3. [3] M.R. Corazao, M.A. Khalaf, L.M. Guerra, M. Potkonjak, and J.M. Rabaey, “Performance optimization using template mapping for datapath-intensive high-level synthesis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.15, no.8, pp.877-888, 1996.
4. [4] W.C. Elmore, “The transient response of damped linear networks with particular regard to wideband amplifiers,” J. Appl. Phys., vol.19, no.1, pp.55-63, 1948.
5. [5] Y. Hagio, M. Yanagisawa, and N. Togawa, “High-level synthesis with post-silicon delay tuning for RDR architectures,” Proc. of International SoC Design Conference, pp.194-197, 2013.
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1. A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017
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