Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers
Author:
Affiliation:
1. Faculty of Engineering, University of Miyazaki
2. Faculty of Environmental Engineering, University of Kitakyushu
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E101.A/5/E101.A_748/_pdf
Reference13 articles.
1. [1] P. Khot and R.B. Shettar, “Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors,” IEEE 19th International Symposium on VLSI Design and Test, pp.1-5, 2015. 10.1109/isvdat.2015.7208121
2. [2] H. Zhuang, Z. Zhu, and Y. Yang, “A 19-nW 0.7-V CMOS voltage reference with no amplifiers and no clock circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.61, no.11, pp.830-834, Nov. 2014. 10.1109/tcsii.2014.2345298
3. [3] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A 2.6nW, 0.45V temperature-compensated subthreshold CMOS voltage reference,” IEEE J. Solid-State Circuits, vol.46, no.2, pp.465-474, Feb. 2011. 10.1109/jssc.2010.2092997
4. [4] A.C. Oliveira, D. Cordova, H.D. Klimach, and S. Bampi, “A 0.45V, 93pW temperature-compensated CMOS voltage reference,” Circuits & Systems (LASCAS), 2017 IEEE 8th Latin American Symposium on, 2017. 10.1109/lascas.2017.7948051
5. [5] B. Chatterjee, N. Modak, A. Amaravati, D. Mistry, D.M. Das, and M.S. Baghini, “Sub-1V, 120nW, PVT-variation tolerant, tunable, and scalable voltage reference with 60-dB PSNA,” IEEE Trans. Nanotechnol., vol.16, no.3, pp.406-4107, May 2017. 10.1109/tnano.2017.2656161
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