On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques-Reference-Cited by-同舟云学术

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques

Published:2011 Issue:12 Volume:E94-A Page:2853-2865
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

CHIM Fu-Shing¹,LAM Tak-Kei¹,WU Yu-Liang¹,FAN Hongbing²

Affiliation:

1. Department of Computer Science and Engineering, The Chinese University of Hong Kong

2. Department of Physics and Computer Science, Wilfrid Laurier University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E94.A/12/E94.A_12_2853/_pdf

Reference31 articles.

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2. [2] W.C. Tang, W.H. Lo, Y.L. Wu, and S.C. Chang, “FPGA technology mapping optimization by rewiring algorithms,” IEEE International Symposium on Circuits and Systems, pp.5653-5656, May 2005.

3. [3] Y.L. Wu, C.C. Cheung, D.I. Cheng, and H. Fan, “Further improve circuit partitioning using GBAW logic perturbation techniques,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.11, no.3, pp.451-460, June 2003.

4. [4] S.C. Chang, K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, “Post-layout logic restructuring using alternative wires,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.16, no.6, pp.587-596, June 1999.

5. [5] S.C. Chang, K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, “Layout driven logic synthesis for FPGAs,” Proc. Design Automation Conference, pp.308-313, June 1994.

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