Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

Author:

SUDA Akihiro1,TAKASE Hideki1,TAKAGI Kazuyoshi1,TAKAGI Naofumi1

Affiliation:

1. Kyoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference11 articles.

1. [1] U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, “A practical automatic polyhedral parallelizer and locality optimizer,” Proc. ACM SIGPLAN Conf. on PLDI, pp.101-113, 2008.

2. [2] U.K.R. Bondhugula, Effective Automatic Parallelization and Locality Optimization Using the Polyhedral Model, Ph.D. thesis, Ohio State University, 2008.

3. [3] A. Darte and F. Vivien, “Optimal fine and medium grain parallelism detection in polyhedral reduced dependence graphs,” Int'l Journal of Parallel Programming, vol.25, no.6, pp.447-496, 1997.

4. [4] Y. Leow, C. Ng, and W. Wong, “Generating hardware from openmp programs,” Proc. Int'l Conf. on FPT, pp.73-80, 2006.

5. [5] G. Wu, Y. Dou, and M. Wang, “Automatic synthesis of processor arrays with local memories on fpgas,” Proc. Int'l Conf. on FPT, pp.249-252, 2010.

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