A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine-Reference-Cited by-同舟云学术

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine

Published:2013 Issue:6 Volume:E96.A Page:1222-1235
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LIAO Hsuan-Chun¹,ASRI Mochamad¹,ISSHIKI Tsuyoshi¹,LI Dongju¹,KUNIEDA Hiroaki¹

Affiliation:

1. Department of Communications and Integrated Systems, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/6/E96.A_1222/_pdf

Reference28 articles.

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