Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches-Reference-Cited by-同舟云学术

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches

Published:2013 Issue:8 Volume:E96.A Page:1712-1722
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

INOUE Keisuke¹,KANEKO Mineo²

Affiliation:

1. Department of Global Information Technology, Kanazawa Technical College (KTC)

2. School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/8/E96.A_1712/_pdf

Reference8 articles.

1. [1] H. Lee, S. Paik, and Y. Shin, “Pulse width allocation and clock skew scheduling: Optimizing sequential circuits based on pulsed latches,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.29, no.3, pp.355-366, March 2010.

2. [2] D. Chinnery, K. Keutzer, J. Sanghavi, E. Killian, and K. Sheth, “Automatic replacement of flip-flops by latches in ASICs,” in Closing the Gap Between ASIC and Custom, pp.187-208, Springer, 2004.

3. [3] T.-Y. Wu and Y.-L. Lin, “Storage optimization by replacing some flip-flops with latches,” Proc. European Design Automation Conference (EURO-DAC), pp.296-301, Sept. 1996.

4. [4] G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, New York, 1994.

5. [5] W. Yang, I.-C. Park, and C.-M. Kyung, “Low-power high-level synthesis using latches,” Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp.462-465, Jan. 2001.