Low-Voltage Wireless Analog CMOS Circuits toward 0.5 V Operation-Reference-Cited by-同舟云学术

Low-Voltage Wireless Analog CMOS Circuits toward 0.5 V Operation

Published:2010 Issue:2 Volume:E93-A Page:356-366
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

MATSUOKA Toshimasa¹,WANG Jun¹,KIHARA Takao¹,HAM Hyunju¹,TANIGUCHI Kenji¹

Affiliation:

1. Osaka University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E93.A/2/E93.A_2_356/_pdf

Reference46 articles.

1. [1] Semiconductor Industry Association, “International technology roadmap for semiconductors 2007 edition.” Available: http://www.itrs.net/

2. [2] A. Matsuzawa, “Analog IC technologies for future wireless systems,” IEICE Trans. Electron., vol.E89-C, no.4, pp.446-454, April 2006.

3. [3] A. Matsuzawa, “Digital-centric RF CMOS technologies,” IEICE Trans. Electron., vol.E91-C, no.11, pp.1720-1725, Nov. 2008.

4. Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

5. [5] H. Kotaki, S. Kakimoto, M. Nakano, T. Matsuoka, K. Adachi, K. Sugimoto, T. Fukushima, and Y. Sato, “Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS,” 1996 International Electron Device Meeting, pp.459-462, San Francisco, Dec. 1996.

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