Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher-Reference-Cited by-同舟云学术

Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher

Published:2010 Issue:1 Volume:E93-A Page:3-12
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

YAMAMOTO Dai¹,YAJIMA Jun¹,ITOH Kouichi¹

Affiliation:

1. FUJITSU LABORATORIES LTD.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E93.A/1/E93.A_1_3/_pdf

Reference27 articles.

1. A survey on sensor networks

2. [2] K. Finkenzeller, RFID handbook: Fundamentals and applications in contactless smart cards and identification second edition, John Wiley & Sons, May 2003.

3. New block encryption algorithm MISTY

4. [4] ISO/IEC18033-3, “Information technology — Security techniques — Encryption algorithms — Part 3: Block ciphers, ” July 2005.

5. [5] T. Ichikawa, T. Sorimachi, and M. Matsui, “A study on hardware design for block encryption algorithms, ” SCIS1997, 9.D, Jan. 1997.

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4. Compact Hardware Implementations of MISTY1 Block Cipher;Journal of Circuits, Systems and Computers;2017-10-30

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